(1) Field of the Invention
The invention belongs to the field of semiconductor manufacturing, and more specifically to the process of creating copper lines using the damascene process.
(2) Background of the Invention
The present invention relates specifically to the Damascene process that is used for the formation of semiconductor devices. Damascene derives its name from the ancient art involving inlaying metal in ceramic or wood for decorative purposes. In Very Large-Scale Integrated circuit applications, the Damascene process refers to a similar structure.
The Damascene process has been demonstrated on a number of applications. The most commonly applied process is first metal or local interconnects. Some early Damascene structures have been achieved using Reactive Ion Etching (RIE) but Chemical Mechanical Planarization (CMP) is used exclusively today. Metal interconnects using Damascene of copper and of aluminum are also being explored.
FIG. 1a gives an overview of the steps of the Damascene process, as follows:
Step 1 shows the formation of the metal plug, PA0 step 2 shows the deposition of the Intra-Level Dielectric, PA0 step 3 shows the formation of the trenches for metal lines, PA0 step 4 shows the deposition of metal to fill the trenches, PA0 step 5 shows the removal of metal from the surface.
The Damascene process is further explained below, the numbers indicated within this explanation refer to the cross section of a Damascene structure that is shown in FIG. 1b.
Referring now specifically to FIG. 1a, step 1, there is shown the formation of a metal via plug 10 within the semiconductor substrate 14 (FIG. 1b). Any micro-scratch present on the surface will fill with metal during subsequent metal deposition and can cause electrical shorts between adjacent via plugs 10 or between electrical lines deposited on top of surface 12. To remove the Damascene residue and to remove the scratch count on the surface 12, surface 12 is polished and buffed after the metal plugs 10 have been deposited.
FIG. 1a, step 2 shows the deposition of the Intra-Level Dielectric (ILD) 16 (FIG. 1b) which can be deposited using Plasma Enhanced CVD (PECVD) technology. Dielectric 16 can, for instance, be SiO.sub.2.
FIG. 1a, step 3 shows the formation of the trenches 22 (FIG. 1b) for the metal lines, these trenches 22 can be formed using Reactive Ion Etching (RIE) technology.
FIG. 1a, step 4 shows the deposition of metal to fill the trenches 22, this process can use either the CVD or a metal flow process. The excess metal on the surface is removed using the CMP process, see FIG. 1a, step 5, and a planar structure 26 with metal inlays 22 in the intra-level dielectric 16 is achieved.
The application of the Damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etching where the Damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale integrated devices.
FIG. 2a shows Prior Art problems encountered when filling a damascene plug 62 with aluminum 64. The plug 62 can be formed in poly silicide 66. A void 60 can develop above the opening of a damascene plug 62 if the opening is relatively narrow and deep, a design characteristic that becomes more common with smaller semiconductor devices. This void 60 is caused by the difficulty experienced in having deep penetrating flow of the metal within the narrow opening. For a shallow or relatively wide plug 62, FIG. 2b, these problems are not experienced. Void 60 (FIG. 2a) also causes planarization problems during subsequent processing steps and can create a reliability issue.
Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices. Even for these applications however, the wolfram plug was still used for contact points in order to avoid damage to the devices.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe. The present invention teaches methods for avoiding the observed phenomenon of damaged copper lines.
The reliability of a metal interconnect is most commonly described by a lifetime experiment on a set of lines to obtain the medium time to failure. The stress experiment involves stressing the lines at high current densities and at elevated temperatures. The failure criterion is typically an electrical open for non-barrier conductors or a predetermined increase in line resistance for barrier metalization.
The mean time to failure is dependent on the line geometry where this failure is directly proportional to the line width and the line thickness. Experimentally, it has been shown that the width dependence is a function of the ratio of the grain size d of the film and the width of the conductor w. As the ratio w/d decreases, the mean time to failure will increase due to the bamboo effect.
U.S. Pat. No. 5,654,245 teaches about the problems encountered in depositing thin lines, particularly where these lines contain copper. It teaches that copper is notorious for (1) its poor adhesion qualities to silicon dioxide, (2) its tendency to readily diffuse through dielectric materials such as silicon dioxide under certain process conditions and contaminate an underlying silicon region, and (3) its resistance to traditional dry-etching patterning methods (RIE or plasma etch).
Conventional methods proposed for placing copper conductors on silicon based substrates are based on t he deposition of a variety of layers where each layer has characteristics of performance or deposition that enhance the use of copper as the major component within conducting lines. This approach has met with limited success and has as yet not resulted in the large-scale adaptation of copper. The present invention circumvents these disadvantages by teaching a method of copper line deposition that solves previous deposition problems by structural stress reducing approach.
U.S. Pat. No. 5,639,697 (Weling et al.) shows a method to form dummy lines, form an insulating layer thereover, and CMP. The dummy lines improve the CMP of the insulating layer.
U.S. Pat. No. 5,618,757 (Bothra et al.) shows a method to form dummy lines, form SOG and etch back SOG.
U.S. Pat. No. 5,770,518 (Shen) show a method to form dummy lines to reduce undercutting.
U.S. Pat. No. 5,633,190 (Sugiyama) and U.S. Pat. No. 4,916,514 (Nowak) show dummy lines to improve insulating layer chemical-mechanical polishing.